Sunday, November 14, 2010

How long does it take to make a context switch?

That's a interesting question I'm willing to spend some of my time on. Someone at StumbleUpon emitted the hypothesis that with all the improvements in the Nehalem architecture (marketed as Intel i7), context switching would be much faster. How would you devise a test to empirically find an answer to this question? How expensive are context switches anyway? (tl;dr answer: very expensive)

The lineup

April 21, 2011 update: I added an "extreme" Nehalem and a low-voltage Westmere.
April 1, 2013 update: Added an Intel Sandy Bridge E5-2620.
I've put 4 different generations of CPUs to test:
  • A dual Intel 5150 (Woodcrest, based on the old "Core" architecture, 2.67GHz). The 5150 is a dual-core, and so in total the machine has 4 cores available. Kernel: 2.6.28-19-server x86_64.
  • A dual Intel E5440 (Harpertown, based on the Penrynn architecture, 2.83GHz). The E5440 is a quad-core so the machine has a total of 8 cores. Kernel: 2.6.24-26-server x86_64.
  • A dual Intel E5520 (Gainestown, based on the Nehalem architecture, aka i7, 2.27GHz). The E5520 is a quad-core, and has HyperThreading enabled, so the machine has a total of 8 cores or 16 "hardware threads". Kernel: 2.6.28-18-generic x86_64.
  • A dual Intel X5550 (Gainestown, based on the Nehalem architecture, aka i7, 2.67GHz). The X5550 is a quad-core, and has HyperThreading enabled, so the machine has a total of 8 cores or 16 "hardware threads". Note: the X5550 is in the "server" product line. This CPU is 3x more expensive than the previous one. Kernel: 2.6.28-15-server x86_64.
  • A dual Intel L5630 (Gulftown, based on the Westmere architecture, aka i7, 2.13GHz). The L5630 is a quad-core, and has HyperThreading enabled, so the machine has a total of 8 cores or 16 "hardware threads". Note: the L5630 is a "low-voltage" CPU. At equal price, this CPU is in theory 16% less powerful than a non-low-voltage CPU. Kernel: 2.6.32-29-server x86_64.
  • A dual Intel E5-2620 (Sandy Bridge-EP, based on the Sandy Bridge architecture, aka E5, 2Ghz). The E5-2620 is a hexa-core, has HyperThreading, so the machine has a total of 12 cores, or 24 "hardware threads". Kernel: 3.4.24 x86_64.
As far as I can say, all CPUs are set to a constant clock rate (no Turbo Boost or anything fancy). All the Linux kernels are those built and distributed by Ubuntu.

First idea: with syscalls (fail)

My first idea was to make a cheap system call many times in a row, time how long it took, and compute the average time spent per syscall. The cheapest system call on Linux these days seems to be gettid. Turns out, this was a naive approach since system calls don't actually cause a full context switch anymore nowadays, the kernel can get away with a "mode switch" (go from user mode to kernel mode, then back to user mode). That's why when I ran my first test program, vmstat wouldn't show a noticeable increase in number of context switches. But this test is interesting too, although it's not what I wanted originally.

Source code: timesyscall.c Results:
  • Intel 5150: 105ns/syscall
  • Intel E5440: 87ns/syscall
  • Intel E5520: 58ns/syscall
  • Intel X5550: 52ns/syscall
  • Intel L5630: 58ns/syscall
  • Intel E5-2620: 67ns/syscall
Now that's nice, more expensive CPUs perform noticeably better (note however the slight increase in cost on Sandy Bridge). But that's not really what we wanted to know. So to test the cost of a context switch, we need to force the kernel to de-schedule the current process and schedule another one instead. And to benchmark the CPU, we need to get the kernel to do nothing but this in a tight loop. How would you do this?

Second idea: with futex

The way I did it was to abuse futex (RTFM). futex is the low level Linux-specific primitive used by most threading libraries to implement blocking operations such as waiting on a contended mutexes, semaphores that run out of permits, condition variables and friends. If you would like to know more, go read Futexes Are Tricky by Ulrich Drepper. Anyways, with a futex, it's easy to suspend and resume processes. What my test does is that it forks off a child process, and the parent and the child take turn waiting on the futex. When the parent waits, the child wakes it up and goes on to wait on the futex, until the parent wakes it and goes on to wait again. Some kind of a ping-pong "I wake you up, you wake me up...".

Source code: timectxsw.c Results:
  • Intel 5150: ~4300ns/context switch
  • Intel E5440: ~3600ns/context switch
  • Intel E5520: ~4500ns/context switch
  • Intel X5550: ~3000ns/context switch
  • Intel L5630: ~3000ns/context switch
  • Intel E5-2620: ~3000ns/context switch
Note: those results include the overhead of the futex system calls.

Now you must take those results with a grain of salt. The micro-benchmark does nothing but context switching. In practice context switching is expensive because it screws up the CPU caches (L1, L2, L3 if you have one, and the TLB – don't forget the TLB!).

CPU affinity

Things are harder to predict in an SMP environment, because the performance can vary wildly depending on whether a task is migrated from one core to another (especially if the migration is across physical CPUs). I ran the benchmarks again but this time I pinned the processes/threads on a single core (or "hardware thread"). The performance speedup is dramatic.

Source code: Results:
  • Intel 5150: ~1900ns/process context switch, ~1700ns/thread context switch
  • Intel E5440: ~1300ns/process context switch, ~1100ns/thread context switch
  • Intel E5520: ~1400ns/process context switch, ~1300ns/thread context switch
  • Intel X5550: ~1300ns/process context switch, ~1100ns/thread context switch
  • Intel L5630: ~1600ns/process context switch, ~1400ns/thread context switch
  • Intel E5-2620: ~1600ns/process context switch, ~1300ns/thread context siwtch
Performance boost: 5150: 66%, E5440: 65-70%, E5520: 50-54%, X5550: 55%, L5630: 45%, E5-2620: 45%.

The performance gap between thread switches and process switches seems to increase with newer CPU generations (5150: 7-8%, E5440: 5-15%, E5520: 11-20%, X5550: 15%, L5630: 13%, E5-2620: 19%). Overall the penalty of switching from one task to another remains very high. Bear in mind that those artificial tests do absolutely zero computation, so they probably have 100% cache hit in L1d and L1i. In the real world, switching between two tasks (threads or processes) typically incurs significantly higher penalties due to cache pollution. But we'll get back to this later.

Threads vs. processes

After producing the numbers above, I quickly criticized Java applications, because it's fairly common to create shitloads of threads in Java, and the cost of context switching becomes high in such applications. Someone retorted that, yes, Java uses lots of threads but threads have become significantly faster and cheaper with the NPTL in Linux 2.6. They said that normally there's no need to do a TLB flush when switching between two threads of the same process. That's true, you can go check the source code of the Linux kernel (switch_mm in mmu_context.h):
static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
                             struct task_struct *tsk)
       unsigned cpu = smp_processor_id();

       if (likely(prev != next)) {
       } else {
               [don't typically reload cr3]
In this code, the kernel expects to be switching between tasks that have different memory structures, in which cases it updates CR3, the register that holds a pointer to the page table. Writing to CR3 automatically causes a TLB flush on x86.

In practice though, with the default kernel scheduler and a busy server-type workload, it's fairly infrequent to go through the code path that skips the call to load_cr3. Plus, different threads tend to have different working sets, so even if you skip this step, you still end up polluting the L1/L2/L3/TLB caches. I re-ran the benchmark above with 2 threads instead of 2 processes (source: timetctxsw.c) but the results aren't significantly different (this varies a lot depending on scheduling and luck, but on average on many runs it's typically only 100ns faster to switch between threads if you don't set a custom CPU affinity).

Indirect costs in context switches: cache pollution

The results above are in line with a paper published a bunch of guys from University of Rochester: Quantifying The Cost of Context Switch. On an unspecified Intel Xeon (the paper was written in 2007, so the CPU was probably not too old), they end up with an average time of 3800ns. They use another method I thought of, which involves writing / reading 1 byte to / from a pipe to block / unblock a couple of processes. I thought that (ab)using futex would be better since futex is essentially exposing some scheduling interface to userland.

The paper goes on to explain the indirect costs involved in context switching, which are due to cache interference. Beyond a certain working set size (about half the size of the L2 cache in their benchmarks), the cost of context switching increases dramatically (by 2 orders of magnitude).

I think this is a more realistic expectation. Not sharing data between threads leads to optimal performance, but it also means that every thread has its own working set and that when a thread is migrated from one core to another (or worse, across physical CPUs), the cache pollution is going to be costly. Unfortunately, when an application has many more active threads than hardware threads, this is happening all the time. That's why not creating more active threads than there are hardware threads available is so important, because in this case it's easier for the Linux scheduler to keep re-scheduling the same threads on the core they last used ("weak affinity").

Having said that, these days, our CPUs have much larger caches, and can even have an L3 cache.
  • 5150: L1i & L1d = 32K each, L2 = 4M
  • E5440: L1i & L1d = 32K each, L2 = 6M
  • E5520: L1i & L1d = 32K each, L2 = 256K/core, L3 = 8M (same for the X5550)
  • L5630: L1i & L1d = 32K each, L2 = 256K/core, L3 = 12M
  • E5-2620: L1i & L1d = 64K each, L2 = 256K/core, L3 = 15M
Note that in the case of the E5520/X5550/L5630 (the ones marketed as "i7") as well as the Sandy Bridge E5-2520, the L2 cache is tiny but there's one L2 cache per core (with HT enabled, this gives us 128K per hardware thread). The L3 cache is shared for all cores that are on each physical CPU.

Having more cores is great, but it also increases the chance that your task be rescheduled onto a different core. The cores have to "migrate" cache lines around, which is expensive. I recommend reading What Every Programmer Should Know About Main Memory by Ulrich Drepper (yes, him again!) to understand more about how this works and the performance penalties involved.

So how does the cost of context switching increase with the size of the working set? This time we'll use another micro-benchmark, timectxswws.c that takes in argument the number of pages to use as a working set. This benchmark is exactly the same as the one used earlier to test the cost of context switching between two processes except that now each process does a memset on the working set, which is shared across both processes. Before starting, the benchmark times how long it takes to write over all the pages in the working set size requested. This time is then discounted from the total time taken by the test. This attempts to estimate the overhead of overwriting pages across context switches.

Here are the results for the 5150:As we can see, the time needed to write a 4K page more than doubles once our working set is bigger than what we can fit in the L1d (32K). The time per context switch keeps going up and up as the working set size increases, but beyond a certain point the benchmark becomes dominated by memory accesses and is no longer actually testing the overhead of a context switch, it's simply testing the performance of the memory subsystem.

Same test, but this time with CPU affinity (both processes pinned on the same core):Oh wow, watch this! It's an order of magnitude faster when pinning both processes on the same core! Because the working set is shared, the working set fits entirely in the 4M L2 cache and cache lines simply need to be transfered from L2 to L1d, instead of being transfered from core to core (potentially across 2 physical CPUs, which is far more expensive than within the same CPU).

Now the results for the i7 processor:Note that this time I covered larger working set sizes, hence the log scale on the X axis.

So yes, context switching on i7 is faster, but only for so long. Real applications (especially Java applications) tend to have large working sets so typically pay the highest price when undergoing a context switch. Other observations about the Nehalem architecture used in the i7:
  • Going from L1 to L2 is almost unnoticeable. It takes about 130ns to write a page with a working set that fits in L1d (32K) and only 180ns when it fits in L2 (256K). In this respect, the L2 on Nehalem is more of a "L1.5", since its latency is simply not comparable to that of the L2 of previous CPU generations.
  • As soon as the working set increases beyond 1024K, the time needed to write a page jumps to 750ns. My theory here is that 1024K = 256 pages = half of the TLB of the core, which is shared by the two HyperThreads. Because now both HyperThreads are fighting for TLB entries, the CPU core is constantly doing page table lookups.
Speaking of TLB, the Nehalem has an interesting architecture. Each core has a 64 entry "L1d TLB" (there's no "L1i TLB") and a unified 512 entry "L2TLB". Both are dynamically allocated between both HyperThreads.


I was wondering how much overhead there is when using virtualization. I repeated the benchmarks for the dual E5440, once in a normal Linux install, once while running the same install inside VMware ESX Server. The result is that, on average, it's 2.5x to 3x more expensive to do a context switch when using virtualization. My guess is that this is due to the fact that the guest OS can't update the page table itself, so when it attempts to change it, the hypervisor intervenes, which causes an extra 2 context switches (one to get inside the hypervisor, one to get out, back to the guest OS).

This probably explains why Intel added the EPT (Extended Page Table) on the Nehalem, since it enables the guest OS to modify its own page table without help of the hypervisor, and the CPU is able to do the end-to-end memory address translation on its own, entirely in hardware (virtual address to "guest-physical" address to physical address).

Parting words

Context switching is expensive. My rule of thumb is that it'll cost you about 30µs of CPU overhead. This seems to be a good worst-case approximation. Applications that create too many threads that are constantly fighting for CPU time (such as Apache's HTTPd or many Java applications) can waste considerable amounts of CPU cycles just to switch back and forth between different threads. I think the sweet spot for optimal CPU use is to have the same number of worker threads as there are hardware threads, and write code in an asynchronous / non-blocking fashion. Asynchronous code tends to be CPU bound, because anything that would block is simply deferred to later, until the blocking operation completes. This means that threads in asynchronous / non-blocking applications are much more likely to use their full time quantum before the kernel scheduler preempts them. And if there's the same number of runnable threads as there are hardware threads, the kernel is very likely to reschedule threads on the same core, which significantly helps performance.

Another hidden cost that severely impacts server-type workloads is that after being switched out, even if your process becomes runnable, it'll have to wait in the kernel's run queue until a CPU core is available for it. Linux kernels are often compiled with HZ=100, which entails that processes are given time slices of 10ms. If your thread has been switched out but becomes runnable almost immediately, and there are 2 other threads before it in the run queue waiting for CPU time, your thread may have to wait up to 20ms in the worst scenario to get CPU time. So depending on the average length of the run queue (which is reflected in load average), and how long your threads typically run before getting switched out again, this can considerably impact performance.

It is illusory to imagine that NPTL or the Nehalem architecture made context switching cheaper in real-world server-type workloads. Default Linux kernels don't do a good job at keeping CPU affinity, even on idle machines. You must explore alternative schedulers or use taskset or cpuset to control affinity yourself. If you're running multiple different CPU-intensive applications on the same server, manually partitioning cores across applications can help you achieve very significant performance gains.


  1. Context switch timing benchmarks have been around for a long time, why not run something like lmbench?

  2. Thanks! I've always wondered what the performance hit would be in a virtual machine environment.

  3. You don't appear to mention if you're testing on a x86 or x86_64 system (as those CPUs can run both). Syscalls are _much_ faster on x86_64.

  4. Benoit,

    I sent you an email to the address listed in your bio. Let me know if you're interested! Thanks,


  5. very interesting blog post, thanks

  6. Leaving on HyperThreading does not give a good indication. HyperThreading does not have a true doubling of hardware threads. There is a probability of contention of the same rare resources. This test should be re-run with HyperThreading disabled to get a look at true numbers. HyperThreading works best when your issue is total throughput, where lazy workloads can better make use of idle areas of the CPU. In a contentious environment with latency sensitivity, HT works against predictability and overall performance when measured as lower latency.

  7. An async server still has context switches, and I mean from a conceptual angle, not a processor angle. A select server still has to change which data structures it is working on. During those events you are switching the context and L2 will need to be switched out.

    And don't forget the other cost, which would be code cleanliness and complexity.

  8. Your conclusion about writing servers in async style versus sync style is not justified by the data. You said yourself that the problem with a context switch is that it trashes your cache. What do you think happens when you submit one async operation and the thread switches to working on another one? Because all the data for the second operation is not in the cache, it has to be faulted in. The effect is the same as the effect of switching to another thread. If data for the second op does not have to be faulted in (i.e. it is already in the cache), then the same would hold for thread-switching and the switch would be inexpensive.

    I can buy that you would not want to have many more CPU-bound threads than hardware threads, but even that conclusion is dubious. If the cost of a context switch is 30 microseconds and the Linux kernel has 1000 time-slices per second, then the most you could be spending on context switches is 30 ms per second, or about three percent of the computer's power. Maybe through other mechanisms the situation is actually worse than this, but without experimentation it will not be easy to be sure.

  9. @Adrian Cockcroft: I didn't use lmbench because I was wondering how to write such a benchmark in the first place, and you always learn more by building things yourself than by using something already existing. My little benchmarks aren't supposed to be alternatives to lmbench, I simply provided the source code so others could unambiguously see how I did the benchmarks and reproduce them.

  10. @Anonymous 1: All the tests happened in an x86_64 environment. I will update the post to reflect this.

  11. @Anonymous 4: I left HyperThreading on because that's what we use on our servers at StumbleUpon (for a variety of reasons). The only "true numbers" are the ones that actually matter for your environment. I know how HT works and the limitations it has, but this isn't relevant to this post.

  12. @Anonymous 5 and James Aguilar: async servers are more likely to perform better than non-async servers. YMWV depending on the type of server we're talking about. At least not doing context switches saves TLB flushes. If you design and implement your multi-threaded server appropriately, you can maximize the performance by using dedicated threads per task type and CPU affinity in order to keep the high cache hit rate that boosts performance so much. Yes it's more work to implement servers this way, but it's the price to pay for the best performance. I changed a server application at StumbleUpon to be fully async non-blocking and I gained from 40% to a full order of magnitude performance boost, depending on the workload.

  13. @James Aguilar: I'm not sure to follow your calculation that leads you to the conclusion that you can't spend more than 3% of your time context switching. I have a MySQL database server running on a dual E7220 = 4 actual cores, it's doing 25k context switches per second, meaning it's doing on average 25000/4=6250 switches per core per second, if each switch takes 30µs, each core is spending 187500µs = 187ms per second doing context switches, which translates in 18.75% of the CPU cycles being wasted switching. In practice though, I'm guessing that this DB doesn't get the full 30µs penalty thanks to shared working set and saved TLB flushes (most of the active threads are part of the same process, so they share the same address space), so we can see 18.75% as the theoretical upper bound of the percentage of CPU cycles wasted to context switching.

  14. What should take more time a context switch or a user-kernel mode switch?

  15. pankaj@tux: this article shows that context switching takes a lot more time than just a simple user-kernel switch (aka mode switch). System calls only do a mode switch.

  16. How to measure the time taken by a single context switch? Is it same for every context switch or it varies?

  17. Thanks a lot! Your investigation helped me great!

  18. This is very helpful. Thanks a lot

  19. Hello,
    your article is very interesting and helpful, thanks!

    I misunderstand something : You're speaking about context switching without specify each time "process context switch" or "thread context switch". For me there is a huge difference, threads share the same virtual space memory. Since threads belong to a same process and a process is executed in 1 processor core (Am I right till here?), can we really have a thread context switch between 2 cores? Or your graphs only represent process context switch?
    I find the difference between threads context switch and process context switch a bit blurred in your explanation.
    Could you explain me?

    Thank you very much

    Yvan Gadeau

  20. It turns out switching between threads and processes isn't significantly different, except in some special cases.

    So you can use them as a representation for either threads or processes (if that answer isn't precise enough for you, please make your own test and post the results! It will be interesting.)

  21. Yes but differences of performances with and without cpu affinity only applies to process context switch and not for thread context switch. Do you agree?

    I don't understand how a thread context switch can occur between 2 threads of different cores.


  22. If you only have two threads on two different cores, then yeah, you're probably not doing context switches (but you could have caching issues)

  23. As far as the Linux kernel's scheduling is concerned, there are no threads or processes. Everything is just a "task".

    If you have a process with one thread, then there is one task that has that PID. If you have a process with three threads, then there are three tasks that share the same PID (but have different TID). But the scheduler doesn't care, all it sees is tasks that want to run, and its goal is to schedule them somewhere.

    The only difference is that when you switch from one task to another, and both tasks share the same virtual address space, then no TLB flush occurs.

    So yes if you have multiple cores (whether they are all in the same physical CPU or you have multiple CPUs), one core could be executing one thread of a process, and the next time quantum could be given to either another thread of that same process, or another process altogether.

    Also possible is the event where one thread is running on a core, and the next time quantum it gets immediately is on another core. This would yield suboptimal performance, especially if both cores are not on the same physical CPU.

  24. Thanks for putting this together.

  25. I liked your post. I do not agree with your final assessment about using 1 software thread per hardware thread. What happens when you are waiting for many ms for a DB to get back to you? Should you just hold up all the other jobs in the queue because you refused to multithread. Threading makes a lot of sense when you take into account the distributed nature of modern architectures.

  26. "What happens when you are waiting for many ms for a DB to get back to you?"
    Use non-blocking i/o, it's better for so many reasons.

  27. @phantomfive In fact Microsoft IOCPs (the one thing I love about Windows, esp. before kqueue/epoll) default to the umber of CPUs, but multiplying by 1.5x if you have anything else that could block mixed in is still better than thousands of threads. See & "The best overall maximum value to pick for the concurrency value is the number of CPUs on the computer. If your transaction required a lengthy computation, a larger concurrency value will allow more threads to run. Each completion packet may take longer to finish, but more completion packets will be processed at the same time. You can experiment with the concurrency value in conjunction with profiling tools to achieve the best effect for your application."

    Interestingly, Solaris and AIX also have something called IOCPs, but I'm not sure how similar they are.

  28. @phantomfive Also, you're assuming it's 'another-IO-bound.' What about when you're really doing something intense in a thread. In that case, you really _do_ want either another pool of threads you talk to via a pipe, or you want some headroom on the # of threads and "experiment" with the concurrency value.

  29. There's links in a HN thread about threads.

    [in the video link] Google measured

    50ns or less "mode switch"
    ~1us minimum context switch - futex, pinned to same core, threads).
    ~3us without pinning

    They looked at the pinned case. Oddly their conclusion was the time is mainly spent running the kernel cpu scheduler.

    Then they showed how to get it down to 200ns without pinning. They want to switch between two threads in the same way your benchmark does. The running one goes to sleep; the sleeping one starts running. They added a new system call that basically just swaps the scheduling state of the two threads (instead of running the full scheduler).

    (In a way it sounds similar to Binder IPC calls on Android